Regviz

Silicon Labs /Series1 /EFM32GG12B /EFM32GG12B510F1024GQ100 /CMU /DPLLCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DPLLCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/Series1/EFM32GG12B/EFM32GG12B510F1024GQ100/CMU/DPLLCTRL#0x0

31282724232019161512118743000000000000000000000000000000000000000000 (MODE)MODE0 (EDGESEL)EDGESEL0 (AUTORECOVER)AUTORECOVER0 (HFXO)REFSEL0 (DITHEN)DITHEN

REFSEL=HFXO

Description

DPLL Control Register

Fields

MODE

Operating Mode Control
EDGESEL

Reference Edge Select
AUTORECOVER

Automatic Recovery Ctrl
REFSEL

Reference Clock Selection Control

0 (HFXO): HFXO selected

1 (LFXO): LFXO selected

2 (USHFRCO): USHFRCO selected

3 (CLKIN0): CLKIN0 selected
DITHEN

Dither Enable Control

Links

()

Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data